Intel is clearly behind rivals TSMC and Samsung with the first generation of extreme ultraviolet lithography (EUV) technology, but it certainly wants to be the first to adopt next-generation EUV tools with a 0.55 NA (or high- NA) which provides higher resolution and productivity. This week, Intel announced that it has ordered its second experimental High-NA tool from ASML.
Intel has announced plans to adopt ASML’s High-NA Twinscan EXE scanners for high-volume manufacturing (HVM) starting in 2025, when the company intends to begin using its 18A manufacturing technology. (~1.8nm). To do this, Intel has been experimenting with High-NA tools since 2018 when it obtained ASML’s Twinscan EXE:5000, the industry’s first EUV scanner with a numerical aperture of 0.55. This week, the company ordered ASML’s next-generation High-NA tool, the Twinscan EXE:5200.
“Compared to current EUV systems, our innovative extended EUV roadmap delivers continuous lithographic improvements at the reduced complexity, cost, cycle time, and energy the chip industry needs to drive a modernization. affordable scale over the next decade,” said ASML President and CTO Martin van den Brink.
High NA EUV tools are crucial for higher resolution (
“Intel’s goal is to remain at the forefront of semiconductor lithography technology and we have strengthened our EUV expertise and capabilities over the past year,” said Dr. Ann Kelleher, Vice Executive President and General Manager of Technology Development at Intel. “Working closely with ASML, we will leverage high-resolution modeling of High-NA EUV as one of the ways to continue Moore’s Law and maintain our strong track record of progressing down to the smallest geometries.”
Just as the adoption of 0.33 NA EUV has not eliminated the use of deep ultraviolet (DUV) lithography, 0.55 NA EUV will not replace existing DUV and EUV tools used in modern factories. . In fact, ASML plans to continue to develop more advanced DUV and 0.33 NA EUV scanners for years to come. Meanwhile, high NA EUV lithography will be a key technology to reduce transistor size and increase transistor density.
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